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-rw-r--r--pyecsca/codegen/simpleserial/Makefile.simpleserial23
1 files changed, 0 insertions, 23 deletions
diff --git a/pyecsca/codegen/simpleserial/Makefile.simpleserial b/pyecsca/codegen/simpleserial/Makefile.simpleserial
index 47a0d1e..1cb855b 100644
--- a/pyecsca/codegen/simpleserial/Makefile.simpleserial
+++ b/pyecsca/codegen/simpleserial/Makefile.simpleserial
@@ -1,26 +1,3 @@
SRC += simpleserial.c
VPATH += :$(FIRMWAREPATH)/simpleserial/
EXTRAINCDIRS += $(FIRMWAREPATH)/simpleserial/
-
-SS_VERS_ALLOWED = SS_VER_1_0 SS_VER_1_1
-
-define SS_VERS_LIST
-
- +---------+--------------+
- | Version | SS_VER value |
- +---------+--------------+
- | V1.0 | SS_VER_1_0 |
- | V1.1 | SS_VER_1_1 |
- +---------+--------------+
-
-endef
-
-# SimpleSerial version
-# To change this, define SS_VER before including this file
-ifeq ($(SS_VER),)
- SS_VER = SS_VER_1_1
-else ifeq ($(filter $(SS_VER),$(SS_VERS_ALLOWED)),)
- $(error Invalid SimpleSerial version: $(SS_VER); allowed verions: $(SS_VERS_LIST))
-endif
-
-CDEFS += -DSS_VER=$(SS_VER) \ No newline at end of file