From f78ff987ac2df62dbd8326ce33ae61c97673710e Mon Sep 17 00:00:00 2001 From: J08nY Date: Wed, 26 Feb 2020 14:28:52 +0100 Subject: Get stuff to work on STM32F0. --- pyecsca/codegen/hal/Makefile.hal | 5 +---- pyecsca/codegen/hal/host/Makefile.host | 1 + pyecsca/codegen/hal/stm32f0/Makefile.stm32f0 | 1 + pyecsca/codegen/hal/stm32f0/stm32f0_hal.c | 5 ++--- pyecsca/codegen/hal/stm32f0/stm32f0_hal_lowlevel.c | 15 +-------------- pyecsca/codegen/hal/stm32f3/Makefile.stm32f3 | 7 ++++--- pyecsca/codegen/hal/xmega/Makefile.xmega | 1 + 7 files changed, 11 insertions(+), 24 deletions(-) (limited to 'pyecsca/codegen/hal') diff --git a/pyecsca/codegen/hal/Makefile.hal b/pyecsca/codegen/hal/Makefile.hal index 3c81d00..186b96e 100644 --- a/pyecsca/codegen/hal/Makefile.hal +++ b/pyecsca/codegen/hal/Makefile.hal @@ -9,7 +9,7 @@ VPATH += :$(HALPATH) #Default stuff EXTRAINCDIRS += $(HALPATH) -PLATFORM_LIST = CW308_STM32F0 CW308_STM32F3 CW308_XMEGA +PLATFORM_LIST = CW308_STM32F0 CW308_STM32F3 CW308_XMEGA HOST define KNOWN_PLATFORMS @@ -27,9 +27,6 @@ endef PLTNAME = Unknown Platform -ifeq ($(DEMO),SECCAN) - CFLAGS += -DSECCAN -endif ifeq ($(MCU_CLK), INT) CFLAGS += -DUSE_INTERNAL_CLK diff --git a/pyecsca/codegen/hal/host/Makefile.host b/pyecsca/codegen/hal/host/Makefile.host index 933c899..1192a78 100644 --- a/pyecsca/codegen/hal/host/Makefile.host +++ b/pyecsca/codegen/hal/host/Makefile.host @@ -5,6 +5,7 @@ EXTRAINCDIRS += $(HALPATH)/host CC = gcc OBJCOPY = objcopy OBJDUMP = objdump +STRIP = strip SIZE = size AR = ar rcs NM = nm \ No newline at end of file diff --git a/pyecsca/codegen/hal/stm32f0/Makefile.stm32f0 b/pyecsca/codegen/hal/stm32f0/Makefile.stm32f0 index c95ce3d..231eafd 100644 --- a/pyecsca/codegen/hal/stm32f0/Makefile.stm32f0 +++ b/pyecsca/codegen/hal/stm32f0/Makefile.stm32f0 @@ -9,6 +9,7 @@ MCU_FLAGS = -mcpu=cortex-m0 CC = arm-none-eabi-gcc OBJCOPY = arm-none-eabi-objcopy OBJDUMP = arm-none-eabi-objdump +STRIP = arm-none-eabi-strip SIZE = arm-none-eabi-size AR = arm-none-eabi-ar rcs NM = arm-none-eabi-nm diff --git a/pyecsca/codegen/hal/stm32f0/stm32f0_hal.c b/pyecsca/codegen/hal/stm32f0/stm32f0_hal.c index 7f09627..ee70dd7 100644 --- a/pyecsca/codegen/hal/stm32f0/stm32f0_hal.c +++ b/pyecsca/codegen/hal/stm32f0/stm32f0_hal.c @@ -23,11 +23,10 @@ void platform_init(void) HAL_RCC_OscConfig(&RCC_OscInitStruct); RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; uint32_t flash_latency = 0; HAL_RCC_ClockConfig(&RCC_ClkInitStruct, flash_latency); #else @@ -61,7 +60,7 @@ void init_uart(void) __HAL_RCC_USART1_CLK_ENABLE(); __HAL_RCC_USART1_CONFIG(RCC_USART1CLKSOURCE_SYSCLK); UartHandle.Instance = USART1; - UartHandle.Init.BaudRate = 38400; + UartHandle.Init.BaudRate = 115200; UartHandle.Init.WordLength = UART_WORDLENGTH_8B; UartHandle.Init.StopBits = UART_STOPBITS_1; UartHandle.Init.Parity = UART_PARITY_NONE; diff --git a/pyecsca/codegen/hal/stm32f0/stm32f0_hal_lowlevel.c b/pyecsca/codegen/hal/stm32f0/stm32f0_hal_lowlevel.c index 554f261..f3870da 100644 --- a/pyecsca/codegen/hal/stm32f0/stm32f0_hal_lowlevel.c +++ b/pyecsca/codegen/hal/stm32f0/stm32f0_hal_lowlevel.c @@ -54,7 +54,7 @@ uint32_t HAL_GetTick(void) #define UART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ -uint32_t SystemCoreClock = 8000000; +uint32_t SystemCoreClock = 7372800; uint32_t HAL_RCC_GetSysClockFreq(void) @@ -67,19 +67,6 @@ uint32_t HAL_RCC_GetPCLK1Freq(void) return 7372800U; } -/** - * @brief Returns the PCLK2 frequency - * @note Each time PCLK2 changes, this function must be called to update the - * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. - * @retval PCLK2 frequency - */ -uint32_t HAL_RCC_GetPCLK2Freq(void) -{ - /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ - //return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]); - return 7372800; -} - /** * @brief Initializes the RCC Oscillators according to the specified parameters in the * RCC_OscInitTypeDef. diff --git a/pyecsca/codegen/hal/stm32f3/Makefile.stm32f3 b/pyecsca/codegen/hal/stm32f3/Makefile.stm32f3 index 5d84aa4..3b9579b 100644 --- a/pyecsca/codegen/hal/stm32f3/Makefile.stm32f3 +++ b/pyecsca/codegen/hal/stm32f3/Makefile.stm32f3 @@ -13,6 +13,7 @@ MCU_FLAGS = -mcpu=cortex-m4 CC = arm-none-eabi-gcc OBJCOPY = arm-none-eabi-objcopy OBJDUMP = arm-none-eabi-objdump +STRIP = arm-none-eabi-strip SIZE = arm-none-eabi-size AR = arm-none-eabi-ar rcs NM = arm-none-eabi-nm @@ -20,9 +21,9 @@ NM = arm-none-eabi-nm #Output Format = Binary for this target FORMAT = binary -CFLAGS += -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -fmessage-length=0 -ffunction-sections -CPPFLAGS += -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -fmessage-length=0 -ffunction-sections -ASFLAGS += -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -fmessage-length=0 -ffunction-sections +CFLAGS += -mthumb -mfloat-abi=soft -mfpu=fpv4-sp-d16 -fmessage-length=0 -ffunction-sections +CPPFLAGS += -mthumb -mfloat-abi=soft -mfpu=fpv4-sp-d16 -fmessage-length=0 -ffunction-sections +ASFLAGS += -mthumb -mfloat-abi=soft -mfpu=fpv4-sp-d16 -fmessage-length=0 -ffunction-sections CDEFS += -DSTM32F303xC -DSTM32F3 -DSTM32 -DDEBUG CPPDEFS += -DSTM32F303xC -DSTM32F3 -DSTM32 -DDEBUG diff --git a/pyecsca/codegen/hal/xmega/Makefile.xmega b/pyecsca/codegen/hal/xmega/Makefile.xmega index 8b7950e..743fca3 100644 --- a/pyecsca/codegen/hal/xmega/Makefile.xmega +++ b/pyecsca/codegen/hal/xmega/Makefile.xmega @@ -8,6 +8,7 @@ CFLAGS += -fpack-struct CC = avr-gcc OBJCOPY = avr-objcopy OBJDUMP = avr-objdump +STRIP = avr-strip SIZE = avr-size AR = avr-ar rcs NM = avr-nm \ No newline at end of file -- cgit v1.3.1