From c8d0bff46001bd5636825c5b0bb4c896cb34a4e6 Mon Sep 17 00:00:00 2001
From: J08nY
Date: Thu, 21 Nov 2019 19:10:50 +0100
Subject: Initialize.

---
 pyecsca/codegen/hal/Makefile.hal | 54 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)
 create mode 100644 pyecsca/codegen/hal/Makefile.hal

(limited to 'pyecsca/codegen/hal/Makefile.hal')

diff --git a/pyecsca/codegen/hal/Makefile.hal b/pyecsca/codegen/hal/Makefile.hal
new file mode 100644
index 0000000..14d4c97
--- /dev/null
+++ b/pyecsca/codegen/hal/Makefile.hal
@@ -0,0 +1,54 @@
+# Processor frequency (external freq-in)
+ifndef F_CPU
+F_CPU = 7372800
+endif
+
+HALPATH = $(FIRMWAREPATH)/hal
+VPATH += :$(HALPATH)
+
+#Default stuff
+EXTRAINCDIRS += $(HALPATH)
+
+PLATFORM_LIST = CW308_STM32F0 CW308_STM32F3 CW308_XMEGA
+
+define KNOWN_PLATFORMS
+
++-------------------------------------------------------+
+| CW308_XMEGA   | CW308T-XMEGA                          |
++-------------------------------------------------------+
+| CW308_STM32F0 | CW308T-STM32F0 (ST Micro STM32F0)     |
++-------------------------------------------------------+
+| CW308_STM32F3 | CW308T-STM32F3 (ST Micro STM32F3)     |
++-------------------------------------------------------+
+
+endef
+
+PLTNAME = Unknown Platform
+
+ifeq ($(DEMO),SECCAN)
+	CFLAGS += -DSECCAN
+endif
+
+ifeq ($(MCU_CLK), INT)
+  CFLAGS += -DUSE_INTERNAL_CLK
+endif
+
+ifeq ($(PLATFORM),CW308_XMEGA)
+#d4 not officially supported, by has same reg map
+  MCU = atxmega128d3
+  HAL = xmega
+  PLTNAME = CW308T: XMEGA Target
+else ifeq ($(PLATFORM),CW308_STM32F0)
+  HAL = stm32f0
+  PLTNAME = CW308T: STM32F0 Target
+else ifeq ($(PLATFORM),CW308_STM32F3)
+  HAL = stm32f3
+  PLTNAME = CW308T: STM32F3 Target
+else
+  $(error Invalid or empty PLATFORM: $(PLATFORM). Known platforms: $(KNOWN_PLATFORMS))
+endif
+
+include $(HALPATH)/$(HAL)/Makefile.$(HAL)
+
+CDEFS += -DHAL=HAL_$(HAL) -DPLATFORM=$(PLATFORM)
+
-- 
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